With great progress of the integrated circuit manufacturing techniques, the device size of the digital logic circuit is developed toward miniaturization. Generally, the digital logic circuit has a plurality of logic gates for collaboratively performing different functions. As the total layout area of the logic gates in the integrated circuit is decreased, the layout area of the digital logic circuit is decreased to achieve the purpose of miniaturization and cost-effectiveness.
FIG. 1A is a schematic circuit diagram illustrating a NAND gate. The NAND gate is composed of two p-channel metal-oxide-semiconductor transistors P1, P2 and two n-channel metal-oxide-semiconductor transistors N1, N2. In a case that the input terminals A and B are both at the high-level state, the output terminal Y is at the low-level state. Whereas, in a case that at least one of the input terminals A and B is at the low-level state, the output terminal Y is at the high-level state.
The cell library of the NAND gate as shown in FIG. 1A has a corresponding standard cell. Therefore, there is a need of providing an improved integrated circuit configuration with enhanced circuit layout flexibility in order to reduce the device size.